1. Technical Field
The present invention relates generally to an improved data processing device. More specifically, the present invention is directed to a clock control hierarchy for integrated microprocessors and systems-on-a-chip in which individual elements of the microprocessors or systems-on-a-chip may be stopped and restarted.
2. Description of Related Art
Highly integrated microprocessor and system-on-a-chip integrated circuits contain many different functional elements. The core logic of microprocessors run with gigahertz clocks. However, when input/output (I/O) and memory devices are incorporated on the same chip, these devices will require different clocking requirements. For a scan based design, i.e. a design in which data is scanned through all of the latch elements of the various functional elements of the microprocessor or system-on-a-chip, the different clocking requirements creates asynchronous boundaries between the core logic and the other functional elements. Scanning across asynchronous clock boundaries is problematic because latch setup and hold times cannot be established reliably between the two clocking environments.
This is especially a problem with debug operations. During debug operations, the desire is to have all digital logic running on the same clock. This will allow the debug engine to scan all latch elements to initialize the chip to a known state. This, however, is not possible with microprocessors or systems-on-a chip that have different clocking domains on the chip. As a result, during debugging, the debug engine must treat each clock domain separately.
During debug operations, it may be desirable to stop one or more functional elements, such as when treating each clock domain separately. For high speed multi-gigahertz systems, such stopping of one or more functional elements may be problematic. This is because known mechanisms require that all of the functional elements be stopped and restarted synchronously. Synchronously stopping the functional elements may require a number of pipeline stages for the instructions in the pipelines of the functional elements to be processed or flushed. For example, in one system architecture, it may take 28 pipeline stages for a functional element to be synchronously stopped. This causes a large overhead with regard to performance of the debug operation when such stopping and restarting of all of the functional elements must be repeated numerous times during a debug operation in order to debug each functional element. No mechanism currently exists for selectively stopping and restarting a functional element individually and asynchronously, with respect to a system clock.